[Dspforum] Lab 7 EDMA questions

[Ryan Merton]

I'm having a very similar problem with this lab as I was having with
the last lab.  I have had tremendous difficulty in getting bits in the
CIPR register to ever become '1'.

I'm using the sample code provided in the lab, and believe I have set
all of the options correctly for the DMA transfer channels.  I observe
that my 'ping' memory buffer has the first two words (ESIZE = 32 bits)
set to 0x00000000, then nothing ever happens after that.  TCINT is set
to 1, and TCC is set to 1.  CIPR1 is never set and the "waitfordma"
loop spins waiting forever.  There appears to be an issue either with
the operation of the DMA or with the McBSP/AIC23 port.

Also, just to double check myself here:  The event to which we are
synchronizing produces a 32-bit word consisted of two packed signed
short values (one for left channel, one for right)?  We then need to
pick one of those channels, convert to float, and zero-pad?

I'll be bringing this in to the lab obviously, but any suggestions you
might have beforehand would be appreciated.

Thanks,
Ryan