[Dspforum] CIPR question

[Nenad Uzunovic]

The way I understood it, the end of opt register (last 4 bits) tells it 
which one of 16 channels to use. Then when CIPR gets set it carries the 
value of the channel that caused interrupt. Therefore, I set these last 
4 bits different for all 3 channels I use (ping, pong, and qdma for 
results).
Please correct me if I am wrong.
Nenad

O'Connor, Sean R. wrote:
> Setting the OPT registers for ping and pong to 0x20320002 and 0x20310002 
> should set CIPR to 2 and 1 when the transfers have completed, I think.  
> CIPR is actually getting set to 6 and 4 respectively, and if I use 6 and 
> 4 as my masks things seem to operate as expected (at least ping and pong 
> get updated and waitfordma() does not hang).  To my knowledge the OPT 
> register is the only register that can effect the CIPR... so this 
> discrepancy is confusing to me.  Any thoughts?
>  
> Thanks,
> Sean
>  
> 
> 
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-- 
Nenad Uzunovic
Robotic Research LLC
nenad at roboticresearch.com
240.631.0008